1. Field of the Invention
The present invention generally relates to methods for forming anisotropic features for high aspect ratio applications. More specifically, the present invention generally relates to methods of forming anisotropic features for high aspect ratio applications by an etch process in semiconductor manufacture.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate pattern is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As the feature sizes have become smaller, the aspect ratio, or the ratio between the depth of the feature and the width of the feature has steadily increased, such that manufacturing processes are being required to etch materials into features having aspect ratios of from about 50:1 to about 100:1 or even greater. Traditionally, features having aspect ratios of about 10:1 or so were produced by anisotropic etching the dielectric layers to a predetermined depth and width. However, when forming higher aspect ratio features, anisotropic etching using conventional sidewall passivation techniques, has become increasingly harder to obtain, thereby resulting in the features having uniform spacing and/or having double or multiple sloped profiles, thus losing the critical dimensions of the features.
Moreover, redeposition or build-up of passivation layers generated during the etching process on the top or sidewall of the features may block the opening defined in a mask. As the mask opening and/or opening of the etching features are narrowed or sealed by the accumulated redeposition layer, the reactive etchants are blocked from penetrating into the opening, thereby limiting the aspect ratio that may be obtained. As such, failure to sufficiently etch the features results in inability to obtain the desired aspect ratio of the features.
Another problem in etching features with high aspect ratio is the occurrence of a microloading effect, which is a measure of the variation in etch dimensions between regions of high and low feature density. The low feature density regions (e.g., isolated regions) receive more reactive etchants per surface area compared to the high feature density regions (e.g., dense regions) due to larger total openings of the surface areas, thereby resulting in a higher etching rate. The sidewall passivation generated from the etch by-products exhibited the similar pattern density dependence where more passivation is formed for the isolated features due to more by-products being generated in the region. The difference in reactants and the passivation per surface area between these two regions increase as feature density difference increase. As shown in FIG. 8A, due to different etch rates and by-products formation in high and low feature density regions, it is often observed that while the low feature density regions 802 have been etched and defined in a certain desired and controlled vertical dimension, the high feature density regions 804 are bowed and/or undercut 806 by the lateral attacking due to the insufficient sidewall passivation. In other processes, the low feature density regions 808 are described being etched at a faster rate with more passivation than the high feature density regions 810, as shown in FIG. 8B, resulting in a tapered top portion 812 on the sidewall of the etched layer 814. Therefore, insufficient sidewall protection associated with the different etch rates in high and low feature density regions with high aspect ratios often results in inability to hold critical dimension of the etch features and poor patterned transfer.
Yet another challenge associated with etching features with high aspect ratios is controlling the etch rate in feature formed through multiple layers and having different feature density. Here, each layer may etch at a different rate depending on feature density. As shown in FIG. 9, faster etch rates in the low feature density regions 902 often results in selectively overetching a layer 904 disposed below the upper etched layer 906, while slower etch rates in the dense feature regions 908 prevents a portion of the layer 910 from being completely etched. As the features move toward even higher aspect ratios, maintaining efficient etching rate over the low and high feature density regions without either underetching the upper layers or overetching into the lower layers has become increasingly difficult to control. The failure to form the features or patterns on the substrate as designed may result in unwanted defects, and further adversely affect subsequent process steps, ultimately degrading or disabling the performance of the final integrated circuit structure.
Therefore, there is a need in the art for improved methods to etch features with high aspect ratios.